Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device.
Description of the Related Art
A substrate formed from a semiconductor such as silicon is provided with elements such as transistors and element isolation portions for electrically isolating them from each other. The element isolation portions are formed from, for example, impurity regions. Impurity regions are formed by forming a resist pattern (a resist film or resist member having openings) on a substrate and then injecting an impurity into the substrate by using the resist pattern. A resist pattern is obtained by forming a resist film on a substrate, exposing desired regions of the resist film, and developing the resist film.
Japanese Patent Laid-Open No. 2011-114063 discloses a technique of forming a resist pattern having a grid-like pattern by exposing twice a grid-like region in a planar view with respect to the upper surface of a substrate, and then developing the resist film. More specifically, in the first exposure, a plurality of linear regions, of the resist film, which extend along the first direction in a planar view are exposed. In the second exposure, a plurality of linear regions extending along the second direction intersecting with the first direction are exposed. This method can reduce the influence of diffracted light which can be generated when exposing the grid-like region at once while exposing the grid-like region by the first and second exposures.
A resist pattern needs to have a sufficient height (thickness) to properly function as a mask when injecting an impurity. On the other hand, in order to achieve higher circuit integration or further miniaturization of elements, it is required to decrease the width of each impurity region or the distance between adjacent impurity regions (miniaturization of impurity regions). For the formation of such impurity regions, for example, it is necessary to decrease the width of a resist pattern.
However, such a resist pattern may collapse before or at the time of injection of an impurity. When a resist pattern collapses, an impurity cannot be properly injected into a substrate, and hence desired impurity regions are not formed. This poses a serious problem when attaining a larger number of pixels while suppressing an increase in pixel region in a solid-state imaging device including a plurality of pixels each partitioned by an impurity region. Note that Japanese Patent Laid-Open No. 2011-114063 gives no consideration to the collapse of a resist pattern described above.